【开发教程6】AI语音人脸识别（会议记录仪／人脸打卡机）-PWM.docx

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1、CC3200AI实验教程疯壳开发板系列W olverine-Team2018/07/1目录1.1 寄存器11.2 实验现象17官网地址：http:/www.fengke.club购买链接：http:官方 QQ 群：193836402PWMPWM (Pulse Width Modulation)即脉冲宽度调制。PWM运用非常的广泛，大到航天飞船,小到便携式USB风扇都可以见到PWM的身影。许多MCU的定时器均带有PWM模式，CC3200也不例外。1.1寄存器CC3200通用定时器支持PWM模式。在PWM模式下，定时器被配置为一个24位的减计数器，初始值在GPTMTnILR和GPTMTnPR寄存器

2、中进行定义。在该模式中，PWM频率和周期是同步事件,这样可以消除毛刺。PWM模式可以通过向寄存器GPTMTnMR中的TnAMS位写入0x01, TnCMR位写入0x00, TnMR位写入0x02。当定时器使能时，装载到定时器寄存器中的值如表1.0.1所示。表1O1装载到定时器的值寄存器向下计数模式向上计数模式GPTMTnRGPTMTnILRGPTMTnVGPTMTnILR当通过软件写GPTMCTL寄存器中的TnEN位时，计数器开始进行减计数直到0。在周期模式中的下一个计数循环，计数器从GPTMTnILR和GPTMTnPR寄存器中装载初始值，并重新开始计数直到通过软件清除GPTMCTL寄存器中的

3、TnEN位进行关闭。该定时器可以通过上升沿、下降沿和边沿触发这3种类型的事件来产生中断。事件类型通过GPTMCTL寄存器中的TnEVENT位来进行配置。中断通过GPTMTnMR寄存器中的TnPEMIE位来进行使能。当事件发生时，GPTMRIS寄存器中的CnERIS位被置位。并且一直保持到通过GPTMICR寄存器来进行清除。如果捕捉模式事件中断通过GPTMIMR寄存器进行使能，则通用定时器也要置位GPTMMIS寄存器中的CnEMIS位。需要注意的是中断状态只有在TnPWMIE被置位时才会更新。另外，通过置位GPTMCTL寄存器中的TnOTE位和GPTMDMAEV寄存器中的CnEDMAEN位使能D

4、MA触发模式,则当TnPWMIE被置位并且发生捕捉时间时，定时器自动产生DMA的触发事件。在PWM模式中，GPTMTnR和GPTMTnV寄存器始终保持相同的值。当计数器的值等于GPTMTnILR和GPTMTnPR寄存器的值时，输出PWM信号，当计数器的值等于GPTMTnMATCHR和GPTMTnPMR寄存器的值时，信号进行翻转。可以通过软件设置GPTMCTL寄存器中的TnPWML位，来对PWM信号的电平进行翻转。这里要注意的是如果PWM输出翻转使能了，那么边沿检测的行为就会相反，本来上升沿有效的，现在就变成了下降沿有效。如图1,0.1就是一个产生PWM信号的例子。OutputSI5dFigur

5、e 9-4. 16-Bit PWM Mode Example图l.O.l产生PWM信号的例子GPTMCFG寄存器配置通用定时器模块的全局操作。确定通用定时器工作于32位模式还是16位模式。该寄存器中的值只能是在GPTMCTL寄存器中的TAEN和TBEN两位被清零时改变。如图1.0.2所示为该寄存器及其位定义。Figure 9-5. GPTMCFG Register31302928272625242322212019181716RESERVEDR-Oh1514131211109876543210RESERVEDGPTMCFGR-OhRM-OhTable 9-9. GPTMCFG Register

6、 Field DescriptionsBitFieldTypoResetDescription31-3RESERVEDROh2-0GPTMCFGR/WOhGPTM Configuration The GPTMCFG values are defined as follows:1h-3h = Reserved 5h - 7h = ReservedOh = For a 16/32-bit timer, this value selects the 32-bit timerconfiguration.4h = For a 16/32-bit timer, this value selects the

7、 16-bit timerconfiguration. The function is controlled by bits 1:0 of GPTMTAMRand GPTMTBMR.图1.0.2 GPTMCFG寄存器及其位定义即把20位写入0,配置为32位定时器模式；写入4,配置为16位定时器模式。GPTMTAMR寄存器的配置是基于GPTMCFG寄存器的配置来进行选择的。在PWM模式中，置位TAAMS位、清除TACMR位和配置TAMR为0x01或者0x02。如图1.0.3所示为GPTMTAMR寄存器，如图104为其位定义。Figure 9-6. GPTMTAMR Register3130292

8、827262524RESERVEDR-Oh2322212019181716RESERVEDR-Oh15141312111098RESERVEDTAPLOTAMRSUTAPWMIETAILDR-OhR/W0hR/W0hR/W-OhR/W-Oh76543210RESERVEDTAMIETACDIRTAAMSTACMIRTAMRR-OhR/W-0hR/WQhR/W-OhR/W-0hR/WQh图103 GPTMTAMR寄存器Table 9-10. GPTMTAMR Register Field DescriptionsBitFieldTypeResetDescription31-12RESERVEDR

9、Oh11TAPLOR/WOhGPTM Timer A PWM Legacy OperationOh = Legacy operation with CCP pin driven Low when theGPTMTAILR is reloaded after the timer reaches 0.1h = CCP is driven High when the GPTMTAILR is reloaded after thetimer reaches 0.10TAMRSUR/WOhGPTM Timer A Match Register Update If the timer is disable

10、d (TAENis clear) when this bit is set. GPTMTAMATCHR and GPTMTAPRare updated when the timer is enabled. If the timer is stalled(TASTALL is set), GPTMTAMATCHR and GPTMTAPR are updatedaccording to the configuration of this bit.Oh = Update the GPTMTAMATCHR register and the GPTMTAPRregister, if used, on

11、the next cycle.1h = Update the GPTMTAMATCHR register and the GPTMTAPRregister, if used, on the next timeout.9TAPWMIER/WOhGPTM Timer A PWM Interrupt Enable This bit enables interrupts inPWM mode on rising, falling, or both edges of the CCP output, asdefined by the TAEVENT field in the GPTMCTL registe

12、r In addition,when this bit is set and a capture event occurs, Timer Aautomatically generates triggers to the DMA if the trigger capability isenabled by setting the TAOTE bit in the GPTMCTL register and theCAEDMAEN bit in the GPTMDMAEV register, respectively. This bitis only valid in PWM mode.Oh = C

13、apture event interrupt is disabled.1h = Capture event interrupt is enabled.Table 9-10. GPTMTAMR Register Field Descriptions (continued)BitFieldTypeResetDescription8TAILDR/WOhGPTM Timer A Interval Load Write Note the state of this bit has noeffect when counting up. The bit descriptions above apply if

14、 the timerts enabled and running. If the timer is disabled (TAEN is dear) whenthis bit is set. GPTMTAR GPTMTAV and GPTMTAPs. are updatedwhen th timer is enabled. If the timer is stalled (TASTALL is set),GPTMTAR and GPTMTAPS are updated according to theconfiguration of this bit.Oh = Update the GPTMTAR and GPTMTAV registers with the valuein the GPTMTAILR register on the next cycle. Also update theGPTMTAPS register with the value in the GPTMTAPR register onthe next cycle1h = Update the GPTMTAR and GPTMTAV registers with