【开发教程4】AI语音人脸识别（会议记录仪／人脸打卡机）-串口.docx

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1、CC3200AI实验教程疯壳开发板系列W olverine-Team2018/07/1：目录1.1 寄存器21.2 实验现象17官网地址：http:/www.fengk/club购买链接：http:官方 QQ 群：193836402串口串行接口分为异步串行接口和同步串行接口两种。异步串行接口统称为通用异步收发器（UART）接口，同步串行接口有SPI和I2C等，同步串行接口除了包含数据线外，还包含时钟线。本次实验中我们使用的是UART,也就是异步串行通信接口。UART的相关标准规定了接口的机械特性、电气特性和功能特性等，UART的电气特性标准包括RS-232C. RS-422、RS-423和RS

2、-485等，其中RS-232c是最常用的串行通信标准。RS-232c是数据终端设备（DTE）和数据通信设备（DCE）之间串行二进制数据交换接口技术标准，其中DTE包括微机、微控制器和打印机等，DCE包括调制解调器MODEM、GSM模块和Wi-Fi模块灯。RS-232C机械特性规定使用25针D型连接器，后来简化为9针D型连接器。RS-232C的电气特性采用负逻辑：逻辑“1”的电平低于-3V,逻辑“0”的电平高于+3V,这个TTL的正逻辑（逻辑“1”表示高电平，逻辑“0”表示低电平）不同，因此通过RS-232c和TTL器件通信时必须进行电平转换。目前微控制器的UART接口采用的是TTL正逻辑，和T

3、TL器件连接不需要电平转换。和采用负逻辑的计算机相连接时需要进行电平转换（我们一般使用USB转串模块）。CC3200包含两个可编程UART接口（UARTA01）,主要特性如下：a、可编程的波特率发生器，允许速度高达3Mbps；b、独立的16*8发送和接口 FIFO,减轻CPU中断处理负载；c、可编程FIFO长度，包括提供传统双缓冲接口的单字节操作；d、FIFO触发阈值包括1/8、1/4、1/2、3/4和7/8；e、标准的异步通信起始、停止和奇偶校验位。CC3200的UART接口具有以下可编程串行接口特性：a、可编程的5、6、7或8位数据；b、偶、奇或无校验生成/检测；c、1或2个停止位生成；d

4、、支持RTS和CTS调制解调器握手；e、标准的FIFO阈值中断和传输结束中断。CC3200的UART支持DMA,使用DMA可实现高效传输,UART具有单独的DMA发送和接收通道。支持当FIFO中有数据的单个请求接收和可编程FIFO阈值的突发请求接收以及FIFO中有空间的单个请求发送和可编程FIFO阈值的突发请求发送。1.1寄存器UARTDR为数据寄存器（也是FIFOs的接口）。在发送数据时，如果FIFO使能了，则写入该寄存器的数据会发送到发送FIFO中。如果FIFO关闭，数据会被存储在发送保持寄存器中（发送FIFO最低一个字）。写该寄存器意味着通过串口发送。在接收数据时，如果FIFO使能了，数

5、据字节和4位状态位被发送到12位宽的接收FIFO中。如果FIFO关闭，数据字节和状态被存储在接收保持寄存器中（接收FIFO中的最低一个字）。可以通过读取该寄存器来获取接收数据。如图1.0.1所示为UARTDR寄存器，如图1.0.2为其位定义。LEGEND: R/W = Read/Write; R = Read only; WltoCI = Write 1 to clear bit; -n = value after reset图1.0.1 UARTDR寄存器Table 6-4. UARTDR Register Field DescriptionsBitFieldTypeResetDescrip

6、tion31-12RESERVEDROh11OEROhUART Overrun ErrorOh = No data has been lost due to a FIFO overrun.1h = New data was received when the FIFO was full, resulting indata loss.10BEROhUART Break ErrorOh = No break condition has occurred1h = A break condition has been detected, indicating that the receivedata

7、input was held Low for longer than a full-word transmission time(defined as start, data, parity, and stop bits).In FIFO mode, this error is associated with the character at the top ofthe FIFO. When a break occurs, only one 0 character is loaded intothe FIFO. The next character is only enabled after

8、the received datainput goes to a 1 (marking state), and the next valid start bit isreceived.9PEROhUART Parity ErrorIn FIFO mode, this error is associated with the character at the top ofthe FIFO.Oh = No parity error has occurred1h = The parity of the received data character does not match theparity

9、defined by bits 2 and 7 of the UARTLCRH register.8FEROhUART Framing ErrorOh = No framing error has occurred1h = The received character does not have a valid stop bit (a validstop bit is 1 ).7-0DATAR/WOhData Transmitted or Received Data that is to be transmitted via theUART is written to this field.

10、When read, this field contains the datathat was received by the UART.图1.0.2 UARTDR寄存器位定义UARTRSR_UARTECR是接收状态寄存器/错误清除寄存器。除了 UARTDR寄存器之外，接收的状态位也可以通过UARTRSR寄存器获取。如果从该寄存器读取状态信息，则状态信息对应与在读取UARTRSR寄存器之前的UARTDR的状态信息。当有溢出条件发生时，状态位中的溢出标志位会立刻被置位。UARTRSR寄存器不能被写。写任何值到寄存器UARTECR中将会清除帧、校验、打断和溢出错官网地址：http:/www.fen

11、Hke.club淘宝店： 官方 QQ 群：1938364023误。复位会清零所有的位。如图103所示为UARTRSR_UARTECR寄存器，如图104为其位定义。3130Figure 6-4. UARTRSRUARTECR Register292827262524RESERVED23222120R-Oh19181716RESERVED15141312ROh111098RESERVED7654R-Oh3210RESERVEDOE OR DATAMMBE OR DATAPE_OR_DATAFE OR DATALEGEND: R/W =R-OhRead/Write; R = Read only;FV

12、W-OhR/W9hWltoCI = Write 1 to clear bit; -n = value after resetR/VWOhR/W-Oh图 1.0.3 UARTRSR_UARTECR 寄存器Table 6-5. UARTRSR_UARTECR Register Field DescriptionsBitFieldTypeResetDescription7-4DATAwOhError ClearA write to this register of any data clears the framing, parity, break,and overrun flags.31-4RES

13、ERVEDROh3OE_OR_DATAR/WOhUART Overrun Error (R) or Error Clear (W)Oh (R) = No data has been lost due to a FIFO overrun.1h (R) = New data was received when the FIFO was full, resulting indata loss.This bit is cleared by a write to UARTECR.The FIFO contents remain valid because no further data is writt

14、enwhen the FIFO is full only the contents of the shift register areoverwritten. The CPU must read the data in order to empty the FIFO.2BE_OR_DATAR/WOhUART Break Error (R) or Error Clear (W)Oh (R) = No break condition has occurred1h (R) = A break condition has been detected, indicating that thereceiv

15、e data input was held Low for longer than a full-wordtransmission time (defined as start, data, parity, and stop bits).This bit is cleared to 0 by a write to UARTECR.In FIFO mode, this error is associated with the character at the top ofthe FIFO. When a break occurs, only one 0 character is loaded intot