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1、串口实验教程疯壳开发板系列WO1verine-Team2018/10/31目录第一节串口硬件电路2第二节UART寄存器42.1 UART介绍42.2 UART寄存器42.2.1 接收缓冲寄存器42.2.2 中断使能寄存器52.2.3 中断识别寄存器/FIFO控制寄存器62.2.4 通信线控制寄存器72.2.5 调制器控制寄存器72.2.6 通信线状态寄存器923寄存器配置讲解11第三节UART实验12 开机测试教程 整板责源介绍 开发环境搭建教程 快速上手教程中峡程 S1M900A通信实验代码及教程 TF11CD屏实唳代码及教程 TP-CaP电容触摸屏实验代码及教程 W25Q128-F1ash
2、实验代码及及教程 OV2640摄像头实验代码及教程 TF-Card接口实验代码及教程 MP3音乐播放实验代码及教程 SRAM实验代码及教程初级教程之主处理器(SJM324X) GPIo实验代码及教程 终端实验代码及教程 定时器实验代码及教程串口实验代玛及教程ADC实验代码及教程I2C实验代码及教程SP1实验代码及教程DMA实验代码及教程FSMC实验代码及教程DCM1实验代码及教程SD1o实验代码及教程USB实验代码及教程初级教程之蓝月以电容器(DA14580)GP1o实验代码及教程中新实验代码及教程定时题实验代码及教程串口实验代码及教程ADC实舱代码及教程I2C实蛤代码及教程SP1实验代码及教
3、程邺阚 STMia源整合 S1MCOM责源整合 Dia1og资源整合OmniViSion资源整合高华教程触凄屏实验打接电话实缝收发短信实验I音乐播放实验I拍照实验手机与手环时间同步实验读取手环步伐卡路里心率满试实验体温监测实验NFC通信实验C1ataSheet数据手册摄像头应用文档 B1EjB牙低功耗应用文档 GSM/GPRS应用文档 MP3相关文档 充电电路相关文档 触黑薜相关文档 TF卡相关文档官网地址：http:WWW.fengke.dub购买链接：http:ShoPII官方QQ群：193836402第一节串口硬件电路串口通过USB口及手环下载调试线引出，连接MCU的P12与P13引脚，
4、如下图所示：J3CaN3DAP.1DAP12-1PGND28DAP13DAP12第二节UART寄存器2.1 UART介绍这个UART符合工业标准16550,并且可以和外围设备串行通信。主设备(CPU)通过APB总线将数据写进UART并且被转换成串行格式并且发送到目标设备。串行数据也可以通过UART被接收存储之后，主设备读取接收的数据。UART模块不支持DMA,但是它有内部FIFOs,并且支持硬件流控制信号(RTS,CTS,DTR,DSR)。UART模块有16字节的发送和接收FIF0；支持硬件流控制(CTS/RTS)；影子寄存器来减少软件开销并且有可编程的软件复位；发送寄存器为空的中断模式；Ir
5、DAI.0S1R模式支持低功耗模式；可编程的字节属性、校验位和停止位(1,1.5,2)；可以断开通信及检测通信线是否断开；中断优先级的识别；可编程的串行通信波特率。2.2 UART寄存器UART相关的寄存器比较多，所以我们只介绍常用的寄存器，其它的可以参考官方数据手册DA14580_DS_v3.1.pdf,位于目录：.WT开发板硬件资料。2.2.1接收缓冲寄存密Tab1e81:UART_RBR_THR_D11_REG(0x50001000)BitModeSymbo1DescriptionReset15:8Reserved0x07:0R/WRBR_THR_D11ReceiveBufferRegi
6、ster:Thisregisterntainsthedatabytereceivedontheseria1inputport(sin)inUARTmodeortheseria1infraredinput(sirJn)ininfraredmode.Thedatainthisregisterisva1idon1yiftheDataReady(DR)bitinthe1inestatusRegister(1SR)isset.IfFIFOsaredisab1ed(FCR(0settozero),thedataintheRBRmustbereadbeforethenextdataarrives,other
7、wiseitwi11beoverwritten,resu1tinginanovernerror.IfFIFOsareenab1ed(FCR(0settoone),thisregisteraccessestheheadofthereceiveFIFO.IfthereceiveFIFOisfu11andthisregisterisnotreadbeforethenextdatacharacterarrives,thenthedataa1readyintheFIFOwi11bepreservedbutanyincomingdatawi11be1ost.Anoverrunerrorwi11a1sooc
8、cur.TransmitHo1dingRegister:Thisregisterctasdatatobetransmittedontheseria1outputport(sout)inUARTmodeortheseria1infraredoutput(sir_out_n)ininfraredmode.Datashou1don1ybewrittentotheTHRwhentheTHREmpty(THRE)bit(1SR5)isset.IfFIFOsaredisab1ed(FCR0settozero)andTHREisset,wr1bgasing1echaractertotheTHRc1earst
9、heTHREAnyadditiona1writestotheTHRbeforetheTHREissetagaincausestheTHRdatatobeoverwritten.IfFIFOsareenab1ed(FCR0settoone)andTHREisset,xnumberofcharactersofdatamaybewrittentotheTHRbeforetheFIFOisfu11.Thenumberx(defau1t=16)isdeteninec1bytheva1ueofFIFODepththatyousetduringnfiguratio.Anyattempttowritedata
10、wentheFIFOisfu11resu1tsinthewritedatabeing1ost.Divisor1atch(1ow):Tisregistermakesupthe1ower8-bitsofa16-bt,rea(Vwrte,Divisor1atcregisterthatntainsthebaudratedivisorfortheUARTTisregistermayon1ybeaccessedwhentheD1ABbit(1CR(7)isset.Theoutputbaudrateisequa1totheseria1dock(SdK)frequencydividedbysixteentim
11、estheva1ueofthebaudratedivisor,asfo11ows:baudrate=(seria1c1ockfreq)/(16*divisor)NotethatwiththeDivisor1atchRegisters(D11andD1H)settozero,thebauddockisdisab1edandnoseria1mmunicatjonswi11occur.A1so,oncetheD11isset,at1east8c1ockcyc1esofthes1owestDW_apb_uartc1ocksh1dbea11owedtopassbeforetransmittingorre
12、ceivingdata0x015:8位：保留不使用;7:0位：接收缓存寄存器。2.2.2 中断使能寄存器Tab1e82:UART_IER_D1H_REG(0x50001004)BitModeSymbo1DescriptionReset-Reserved0x0RPTIME_D1H7InterruptEnab1eRegister:PTIME,Programmab1eTHREInterruptModeEnab1e.T1sisusedtoenab1e/dIsab1ethegenerationofTHREInterrupt.0=disab1ed1=enab1edDivisor1atch(High):Bi
13、tofthe8bitD1Hregister0x0-Reserved003R/WEDSSI_D1H3InterruptEnab1eRegisterEDSSI,Enab1eModemStatusInterrupt.ThisisusedtoenatHe/disab1ethegenerationofModemStatusInterrupt.Thisistefourthhighestpriorityinterrupt.0=disab1ed1=enab1edDivisor1atc(High):Bit3ofthe8bitD1Hregister002R/WE1SI_DH12InterruptEnab1eReg
14、isterE1SI,Enab1eReceiver1ineStatusIntemipt.Thisisusedtoenab1e/disab1ethegenerationofReceiver1ineStatusIntenrupt.Thisisthehighestpriorityntept.0=disab1ed1=enab1edDivisor1atc(High):B1t(2ofthe8bitD1Hregister.0x0R/WETBEI_D1H1InterruptEnab1eRegister:ETBEI,Enab1eTransmitHo1dingRegisterEmptyInterruptTisisu
15、sedtoenab1e/disab1ethegenerationOfTransmitterHo1dingRegisterEmptyInterruptThisisthethirdhighestpriorityinterrupt.0=disab1ed1=enab1edDivisor1atch(High):Bt1ofthe8bitD1Hregister.0x00R/WERBFI_D1H0InterruptEnab1eRegister:ERBFI,Enab1eReceivedDataAvai1ab1eInterrupt.Thisisusedtoenab1e/disab1ethegenerationofReceivedDataAvai1ab1eInterru
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